As the processing speed of microprocessors increases, the demand for memory devices having faster access times also increases. Additionally, the demand for memory devices that are designed for low voltage operation has also increased with the popularity of portable computing devices, which are typically battery operated. Memory system designers have developed methods and designs that shave off nanoseconds from access times in order to satisfy the demand for high speed memory devices while operating under low voltage conditions. Even with the advances made in memory device designs, the fundamental building blocks of memory devices have remained relatively the same. As will be described in more detail below, these building blocks are the basic elements that are shared among all types of memory devices, regardless of whether they are synchronous or asynchronous, random-access or read-only, or static or dynamic.
A conventional memory device is illustrated in FIG. 1. The memory device includes an address register 12 that receives either a row address or a column address on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory bank arrays 20 and 22 depending upon the state of a bank address bit forming part of the row address. The arrays 20 and 22 are comprised of memory cells arranged in rows and columns. Associated with each of the arrays 20 and 22 is a respective row address latch 26, which stores the row address, and a row decoder 28, which applies various signals to its respective array 20 or 22 as a function of the stored row address.
After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. The column address latch 40 momentarily stores the column address while it is provided to the column address buffer 44. The column address buffer 44 applies a column address to a column decoder 48, which applies various column signals to respective sense amplifiers and associated column circuits 50 and 52 for the respective arrays 20 and 22.
Data to be read from one of the arrays 20 or 22 are coupled from the arrays 20 or 22, respectively, to a data bus 58 through the column circuit 50 or 52, respectively, and a read data path that includes a data output buffer 56. Data to be written to one of the arrays 20 or 22 are coupled from the data bus 58 through a write data path, including a data input buffer 60, to one of the column circuits 50 or 52 where they are transferred to one of the arrays 20 or 22, respectively.
The above-described operation of the memory device 10 is controlled by a command decoder 68 responsive to high level command signals received on a control bus 70. These high level command signals, which are typically generated by the memory controller, are a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, where the “*” designates the signal as active low. The command decoder 68 generates a sequence of command signals responsive to the high level command signals to carry out a function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
As mentioned above, read data are coupled from one of the arrays 20 and 22 to the data bus 58 through a read data path that is shown in greater detail in FIG. 2. FIG. 2 illustrates a conventional data path 100 for a memory device. The data path 100 is coupled through the column decoder 48 and sense amplifiers 112 to the memory cell array 20 that is arranged in rows and columns of memory cells. Only the memory cell array 20 of FIG. 1 is illustrated in order to reduce the complexity of FIG. 2, to which reference will be made in describing the operation of the data path 100. Additionally, as known in the art, the sense amplifiers 112, although not specifically shown in FIG. 1, are typically included in the sense amplifiers and associated column circuits 50 and 52.
Each of the columns of memory cells of the memory cell array 20 is represented by a pair of digit lines coupled to a respective one of the sense amplifiers 112. As known in the art, when the memory cell array 20 is accessed, a row of memory cells (not shown) are activated, and the sense amplifiers 112 amplify data for the respective column by coupling each of the digit lines of the selected column to voltage supplies such that the digit lines have a complementary logic levels. The column decoder 48 then selects one of the columns of memory cells to be coupled to a local input-output (LIO) line 116 of the data path 100 based on a column address. The LIO 116 is represented by a pair of signal lines, each of which is coupled to a respective one of the pair of digit lines by the column decoder 108. At the time the selected column is coupled to the LIO 116, the signal lines of the LIO 116 are precharged to an internal supply voltage VINT through PMOS transistors 120 and 122. A section selection signal SEC activates pass gates 130 and 132 to couple the LIO 116 to global input/output (GIO) line 140. The GIO 140 is represented by a pair of signal lines, which are coupled to a respective one of the pair of signal lines of the LIO 116. PMOS transistors 144 and 146 couple the signal lines of the GIO 140 to the VINT supply for precharging. As discussed in more detail below, since the data path 100 is based on current mode sensing, the signal lines of the LIO 116 and the GIO 140 are coupled to the VINT supply to prevent significant voltage variations of the LIO 116 and GIO 140 when data read from the memory cell array 20 is coupled to the LIO 116 and GIO 140.
A current sense amplifier 150 is coupled to the GIO 140 to sense a current difference between the signal lines of the GIO 140 and generate voltage output signals CLAT and CLAT— in response to the current difference. The output signals CLAT and CLAT— have complementary logic levels, CLAT being the “true” logic level and CLAT— being the “not true” logic level, as indicated by the underscore “—”. The CLAT and CLAT— signals are coupled to a conventional output buffer to provide an output data signal at an external data terminal. The current sense amplifier 150 includes a pair of PMOS transistors 154, 156 for coupling respective signal lines of the GIO 140 to the VINT supply, and further includes a pair of cross coupled PMOS transistors 160, 164 and a pair of diode coupled NMOS transistors 170, 174 coupled to a drain of a respective PMOS transistor 160, 164. The CLAT and CLAT— output signals are taken from output nodes 180, 184 corresponding to the drain of the PMOS transistors 160, 164. Coupled to the sources of the NMOS transistors 170, 174 is a NMOS selection transistor 180 for coupling the NMOS transistors 170, 174 to ground in response to an active selection signal SEL. It will be appreciated that FIG. 1 is a partial functional block diagram and is provided by way of example, and other functional blocks have been omitted from the data path 100 to avoid overcomplicating the description of operating the data path 100.
In operation, when a memory cell is read, a selected pair of digit lines of a column of memory is coupled to the LIO 116 by the column decoder 48 and the pass-gates 130, 132 are activated to couple the LIO 116 to the GIO 140, as known. A current difference is created in the pairs of signals lines in response to the data state of the memory cell being read. The current difference is detected by the current sense amplifier 150 by creating a current imbalance in the PMOS/diode coupled NMOS legs 160, 170 and 164, 174. The current imbalance results in a voltage difference at the respective output nodes 180, 184, which is further amplified as one of the cross coupled PMOS transistors 160, 164 becomes saturated and the other becomes cutoff. In this manner, the CLAT and CLAT— signals achieve complementary logic levels.
Typically, the GIO lines 140 are physically long signal lines that are routed over the memory device to selectively couple, based on the selective activation of the SEC signal, physically shorter LIO lines 116 to a respective current sense amplifier 150. As a result, the GIO 140 have considerable line impedance that can significantly increase the time for sensing read data from the memory cell array 20 when voltage mode sensing is used. The current mode operation of the data path 100 has the advantage of avoiding the need to drive the signal lines of the GIO 140 to two voltage extremes as in the case for voltage mode sensing. Additionally, current mode operation allows for the voltage levels between the pairs of signal lines for the LIO 116, as well as the signal lines of the GIO 140, to be maintained at a relatively constant voltage. Thus, precharging and equilibrating time for the signal lines of the LIO 116, and of the GIO 140, can be shortened relative to memory devices employing voltage mode operation. As a result, access times can be shortened as well.
Conventional current mode data paths, such as the data path 100, however, suffer when operated at low internal voltage levels. In order to operate properly, the data path 100 requires that the VINT voltage level is greater than the total voltage drop across the LIO 116, the GIO 140, and the PMOS/diode coupled NMOS legs 160, 170 or 164, 174. The voltage drop across the LIO 116 result from coupling a pair of digit lines to the respective signal lines of the LIO 116, and the voltage drop across the GIO 140 includes the voltage drop across the pass gates 130, 132, the precharge PMOS transistors 144, 146, and inherent line resistance of the typically lengthy signal lines of the GIO 140. The voltage drop across the PMOS/diode coupled NMOS legs 160, 170 or 164, 174, is (Vtp+Vdpsat)+(Vtn+Vdnsat), where Vtp is the threshold voltage of the PMOS transistors 160, 164, Vdpsat is the saturation voltage of the PMOS transistors 160, 164, Vtn is the threshold voltage of the NMOS transistors 170, 174, and Vtnsat is the saturation voltage of the NMOS transistors 170, 174.
When using typical operating currents and device characteristics for the data path 100, operation at a voltage level of 1.5 volts is satisfactory. However, where it is desirable to implement the data path 100 under operating conditions having voltage levels approaching 1.0 volts, the data path 100 may not consistently or accurately sense data read from the memory cell array 104. As a result, a read error occurs. Therefore, there is a need for a data path that can accurately and consistently sense read data under low voltage operating conditions.